The Effect of Pipeline Depth on Logic Soft Errors

Soft errors arising from particle strikes to combinational logic circuits can be masked logically (by dominant inputs), electrically (the pulse is too weak to flip a node), or by opportune timing (the transient pulse arrives at a downstream latch when the latch is opaque). The latter effect—timing-window masking—is commonly approximated analytically by computing the ratio of the length of the latching window to the cycle time. This paper identifies the shortcomings of this analytical approach, and highlights the potential for drawing an intuitively attractive but incorrect conclusion from such a model: that deeplypipelined, high-frequency circuits are increasingly vulnerable to logic soft errors. We show empirically that this is not the case, and advocate the use of mean work to failure, or MWTF, instead of MTTF, to accurately describe the vulnerability of pipelined circuits. Furthermore, we identify a second-order effect—SET fanout—which increases the error-resilience of deep pipelines over their shallower counterparts, in effect reversing the previously-held intuition.